1. Field of the Invention
This invention relates to a semiconductor memory device and a method of controlling the semiconductor memory device, and more particularly to a word-line driver.
2. Description of the Related Art
A NAND flash memory includes a plurality of nonvolatile memory cells. Each memory cell is, for example, an n-type MOS transistor with a stacked gate including, for example, a charge storage layer and a control gate. To write data to, or read or erase it from, a memory cell, a specific must be applied to the control gate of the memory cell functioning as a word line. Writing data particularly needs a high voltage, such as voltage Vpgm. The voltage Vpgm is transferred by the row decoder to the selected word line. The voltage Vpgm is a high voltage necessary to inject electrons into the charge storage layer by FN Tunneling.
The row decoder includes an n-type MOS transistor which transfers the voltage Vpgm to a word line. The row decoder further includes a p-type MOS transistor which functions as a switch for transferring a voltage Vpgmh higher than the voltage Vpgm to the gate of the n-type MOS transistor. The row decoder turns the p-type MOS transistor on or off as needed. When the p-type MOS transistor is on, the voltage Vpgmh transferred by the p-type MOS transistor is applied to the gate of the n-type transistor, enabling the n-type transistor to transfer the voltage Vpgm to a word line. This is disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2002-63795. In this case, since zero potential is applied to the gate of the p-type MOS transistor, a high stress due to Vpgmh is applied between the gate and channel of the p-type MOS transistor, that is, to the gate insulating film. Accordingly, continuing to apply zero potential to the gate of the p-type MOS transistor for a long time has been known to cause deterioration of the p-type MOS transistor, making the row decoder circuit as a whole unstable.
To make the p-type MOS transistor less likely to deteriorate, measures can be taken such as reducing the maximum voltage applied to the gate of the p-type MOS transistor, changing the design rules of the MOS transistor, or using multiple p-type MOS transistors in parallel.
However, even with the above measures in place, progress in multilevel NAND flash memories entails increasing Vpgm and Vpgmh. Specifically, since the voltage Vpgmh applied to the gate of the p-type MOS transistor is high, using multiple p-type MOS transistors in parallel to reduce the load on individual transistors through time division is approaching its limit. Furthermore, the parallel arrangement makes the circuit very large; that is, the change in transistor design rules has also reached its limit.